1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of MIS (Metal Insulator-Semiconductor) transistors with different electric characteristics and a manufacturing method thereof.
2. Description of the Background Art
As a method for improving system performance, System on Chip technology has been actively researched and developed recently. A device particularly drawing attention is a DRAM mixed logic memory device in which a memory portion with large capacity and a logic portion operating at high speed are mounted on a single chip.
In the DRAM mixed logic memory device, an MIS transistor is one of technically important key devices. Specifically, in the DRAM memory cell portion, the MIS transistor must be very small to minimize the size of the memory cell and must include an insulation film capable of enduring high voltage application to accommodate a voltage of a word line of a level higher than power supply voltage.
Conversely, in the DRAM logic portion, as high-speed operation is required, a gate electrode interconnection and source/drain active regions must have low resistance and high current driving capability.
To meet the above described conflicting requirements in the DRAM mixed logic memory device is not easy, and generally the performance of the MIS transistor in the DRAM logic portion is lowered to be equal to the performance of the MIS transistor in the DRAM memory cell portion.
FIGS. 14A and 14B show sectional structures of N type MIS transistors, respectively in the memory cell portion and the logic portion mounted on separate chips according to a conventional art.
Shown in FIGS. 14A and 14B are, a semiconductor substrate 1a, a P type well region 2a, a trench isolation region 3a, gate insulation films 4a and 4b of silicon oxide films or the like, a first polycrystalline silicon film 5a of a polycrystalline silicon film doped with an N type impurity or the like, a second polycrystalline silicon film 5b of an N type polycrystalline silicon film doped with an impurity by ion implantation after the formation of the polycrystalline silicon film, a first silicide layer 6a of a tungsten silicide (WxSiy) layer or the like, a second silicide layer 6b of a titanium silicide, (TixSiy) layer, cobalt silicide (CoxSiy) layer or the like, N- source/drain active regions 7a, an extension region 7b, N+ source/drain active regions 8a, insulation films 9a and 9c of a silicon nitride film, a silicon nitrided oxide insulation film, or the like, an insulation film 9b of a silicon nitrided oxide film, a silicon oxide film (both will be referred to as silicon oxide film hereinafter) or the like, and a third silicide layer 10 of a titanium silicide (TixSiy) layer, a cobalt silicide (CoxSiy) layer or the like formed as a silicide layer on the active region.
First polycrystalline silicon film 5a and first silicide layer 6a form a gate electrode of a first MIS transistor of the memory cell portion. Second polycrystalline silicon film 5b and second silicide layer 6b form a gate electrode of a second MIS transistor of the logic portion.
Insulation film 9c covers the gate electrode of the first MIS transistor of the memory cell portion and insulation film 9b is a sidewall.
In general, the performance of the MIS transistor is improved with a thinner gate insulation film. On the other hand, when the gate insulation film is thin, a voltage applied to the gate is lowered to guarantee the reliability. Therefore, in the memory cell portion where high voltage operation is required, thick gate insulation film 4a is formed whereas in the logic portion where maintenance of a certain level of the performance rather than the high voltage operation is required, thin gate insulation film 4b is formed.
In addition, as the logic portion rather than the memory cell portion must operate at fast speed, a material employed in a silicide has a lower sheet resistance at an electrode interconnection in the logic portion than in the memory cell portion. Additionally, the active region is formed of a silicide to suppress the delay of the transistor operation caused by parasitic resistance.
With reference to FIGS. 15A and 15B, sectional structures of the memory cell portion and the logic portion of the DRAM chip having the above described DRAM mixed logic memory will be described. In the drawings, though the structure is shown only up to a level of a first metal interconnection 26 (described below) for the simplicity, generally about two to six layers of metal interconnections are employed besides first metal interconnection 26.
The memory cell portion shown in FIG. 15A includes, a bit line 21 formed of polycrystalline silicon, a polycide or the like, a storage node 22 formed of polycrystalline silicon or the like, a capacitor dielectric film 23 formed of a silicon oxide film, a silicon nitrided oxide film or the like, and a cell plate 24 formed of polycrystalline silicon or the like. In addition, the structure includes interlayer insulation films 28a, 29 and 30.
In the logic portion shown in FIG. 15B, an N type MIS transistor region 25n of a second MIS transistor and a P type MIS transistor region 25p of a third MIS transistor are arranged. Further, in P type MIS transistor region 25p, a third polycrystalline silicon film 5c of a P type polycrystalline silicon film doped with an impurity through ion implantation after the formation of the polycrystalline silicon film and a second silicide layer 6c of a silicide layer formed on third polycrystalline silicon film 5c are formed. Still further, in P type MIS transistor region 25p, a first metal interconnection 26, and metal plugs 27 connecting first metal interconnection 26 and the active region, and first metal interconnection 26 and the gate electrode (not shown) of the transistor are formed. In some cases, first metal interconnection 26 and metal plug 27 are employed also in the memory cell portion. An interlayer insulation film 28b is also provided.
Next, a method for manufacturing first and second MIS transistors in a memory cell portion and a logic portion of a DRAM mixed logic memory will be described. Here the manufacturing processes up to the formation of interlayer insulation film 28a shown in FIG. 15 will be described and the process after the formation of interlayer insulation film 28a will not be described. In addition, as a manufacturing process of a third MIS transistor, which is a P type MIS transistor, is the same with that of first and second MIS transistor, the description thereof will not be repeated.
With reference to FIG. 16, P type well region 2a and an N type well region 2c (see FIG. 15) are formed on semiconductor substrate 1a.
Then, trench isolation region 3a is formed in a region reaching a certain depth from a surface of P type well region 2a. After the memory cell portion is covered by a resist film 32, a silicon oxide film is formed as gate insulation film 4b of the logic portion in the thickness range of about 2 to 4 nm. Thereafter polycrystalline silicon film 5b not doped with an impurity and a silicon oxide film 31 are formed.
Then, anisotropic etching is performed on silicon oxide film 31 by the photolithography technique. Thereafter anisotropic etching is performed on polycrystalline silicon film 5b and gate insulation film 4b using silicon oxide film 31 as a mask, and the gate electrode pattern of the logic portion is formed.
Then implantation of an n type impurity is performed respectively on the N type MIS transistor and P type MIS transistor of the logic portion, forming n type extension region 7b and an n type extension region 7c (see FIG. 15).
As shown in FIG. 17, after the removal of silicon oxide film 31 on the gate electrode through the wet etching or the like, insulation film 4a of a silicon oxide film or the like is formed. In addition, sidewall 9b of the MIS transistor in the logic portion is formed through etchback technique. Here, through the wet etching or the like, silicon oxide film 31 on the gate electrode has been previously removed.
Then, through N+ implantation for forming'source/drain of the N type MIS transistor in the logic portion, N+ source/drain active region 8a is formed and through P+ implantation for source/drain of the P type MIS transistor, a P+ source/drain active region 8b (see FIG. 15) is formed. Here an N type impurity similar to that in the active region is implanted into polycrystalline silicon layer 5b of the gate electrode of the N type MIS transistor in the logic portion. P type impurity is implanted to the P type MIS transistor in the same manner.
Then after the removal of resist film 32, gate insulation film 4a of the memory cell portion is formed. For example, a silicon oxide film of about 7 to 10 nm thickness is formed.
Next with reference to FIG. 18, first polycrystalline silicon film 5a of a doped polycrystalline silicon film, first silicide layer 6a of a tungsten silicide layer and insulation film 9a of a silicon nitrided oxide film are formed. Thereafter, a resist 33 is formed through the photolithography technique in a portion that is to be the gate electrode of the memory cell portion as shown in the figure.
With reference to FIG. 19, anisotropic etching is performed on insulating film 9a and first polycrystalline silicon film 5a using resist 33 as a mask, and a gate electrode pattern of the memory cell portion is formed. Then an N type impurity is implanted to the memory cell portion. FIG. 19 shows portions after the N- implantation for source/drain.
Next with reference to FIG. 20, insulation film 9c of a silicon nitrided oxide film or the like is formed and is removed in the portion other than the portion corresponding to the memory cell portion through the photolithography technique and etching technique.
Then through sputtering of cobalt (Co), a portion of source/drain region 7b and a portion of second polycrystalline silicon film 5b of the gate electrode in the logic portion are turned into a silicide. Thus, second silicide layer 6b and third silicide layer 10 are formed as shown in FIG. 20. By the following formation of first metal interconnection 26, metal plug 27 and interlayer insulation films 28a, 29, and 30, the DRAM mixed logic memory as shown in FIG. 15 is finished.
The DRAM mixed logic memory device as described above has the following four problems.
First, as the MIS transistor of the memory cell portion is formed after the formation of the MIS transistor in the logic portion, polycrystalline silicon produced at the formation of the gate electrode of the MIS transistor in the memory cell portion is left in the logic portion as a residue. This residual polycrystalline silicon causes an electrical short circuit or the like. As shown in FIG. 19, for example, a polycrystalline silicon residue 34a is left in the proximity of a lower portion of sidewall 9b of the MIS transistor in the logic portion.
Secondly, as the gate electrode structure is different in the memory cell portion and the logic portion, the gate electrode of the memory cell portion is formed after the formation of the source/drain active regions and the gate electrode of the logic portion. Therefore because of the previous formation of the MIS transistor in the logic portion, the effect of heat treatment and impurity diffusion is enhanced at the formation of the MIS transistor of the memory cell portion, and hence a substantial interval between the source/drain active regions become decreased. Therefore, compared with a structure in which each logic is formed separately, it is difficult to shorten the gate length of the logic portion.
Thirdly, as mentioned in the description of the second problem, as unintended extra heat is applied on the device compared with the case in which the DRAM or the logic is formed separately, the DRAM in which use of an ultra small transistor is required cannot be formed prior to the formation of the gate electrode of the logic portion.
Therefore during the etching process for the formation of the gate electrode of the MIS transistor in the logic portion, a surface of the semiconductor substrate in the memory cell portion is affected, for example being damaged by the etching. Thus, a leakage current generated in a storage node region of each memory cell is increased. In view of the structure of the memory cell of the DRAM, the suppression of the leakage current is prerequisite and the condition of leakage current suppression is more stringent in the logic portion.
Fourthly, because of the above described first to third problems, the above described MIS transistor cannot be employed in the DRAM mixed logic memory device in practice. As a result, gate insulation films with different thickness are employed in the memory cell portion and the logic portion, and doped polycrystalline silicon and tungsten silicide are employed for the gate electrode of the logic portion as the common material with the memory cell portion.
Therefore compared with the chip in which a logic is formed separately, sheet resistance of the gate electrode interconnection and the active region in the logic portion are high. In addition, as the P type MIS transistor includes a gate electrode of N type polycrystalline silicon with lower performance than a gate electrode of P type polycrystalline silicon, in other words, as the P type MIS transistor is of a buried channel type with lower performance than a surface channel type, the operation speed of the transistor is not satisfactory.